my ideas in action

Category Archives: analog design

new lessons on analog CMOS design

Recently I’m working on some free lessons / courses on electronics.

More specifically on custom analog CMOS design.

I think is better to share my knowledge with others. I try to present detailed design with accent on the principle, methods and trade-offs.

My first is about designing a CMOS analog opamp , with full rail-to-rail inputs and outputs.

I go from easy to hard and I hope to be easy for everyone to understand reasons and the decisions that are made during design process.


For the moment I have only few 10 minutes video…. I will add more soon.



Lab power supply with PIC microcontroller (4)

I made some small changes to the schematic. I added a zener to protect the voltage feedback into Vloop opamp.

Also I changed the way the current limitation loop take over the voltage loop. Previously I was thinking to lower the REF voltage when the ILIM is reached. I think a better way is to use 2wo diodes ( 1N4148) and a 5K resistor to make a OR function. This works better and the transition is smooth. I was looking also at similar power supply from big brands ( Agilent, HP) and they do the same thing.

The new version is 3.1:

LabPicPowerSupply_v3.1_sch ,


LabPicPowerSupply_v3.1_pcb .

I made also an experiment to see hot the etching process works and how good are the tracks. I am disappointed somehow since I did not used a toner transfer but a simple permanent marker. The copper was partially etched on the areas where the marker was thin only.  Where it was thick it is ok. To etch I used hydrochloric acid (HCL 25%)  and oxygenated water (H2O2  10%)

I didn’t had access to a laser printer but I hope so make a full size experiment soon with toner on the real PCB.




Lab power supply with PIC microcontroller (3)

I have some updates regarding my project.

First of all, I have a limited time to work on this project. So it is normal to take such long time to develop it.

Second I do not want to jump too fast in “making” phase and I prefer to go slowly step by step to get a good result.

So, I was worried about the stability of my previous schematic. So after a few hours on spice simulation I understand what was the problem. Well, the main issue is that the voltage loop contained 3 low frequency poles.

One is the opamp itself that has a dominant pole at ~10Hz ( see MCP6022 spec), this cannot be avoided since any opamp will have a pole approx in this range.

The second is the output node. The main issue with this pole is that is moving with the load ( R and C) and since this is a lab power supply it will always be different.So what I decided to do is to use a small output capacitance of 1-10uF and to use a dummy load of approx 10mA. This will force the output NPN ( 2N3055) to have a minimum current even if there is no load. The main reason is that when the current is very small in the 2N3055 transistor the predriver ( BC139) will have almost no current. So the gain drops dramatically and the loop become unstable.

The other pole is at the gate of the predriver NPN . this is a “design” fault since the internal node should not affect the functionality.

So I decided to change the loop architecture and to use a intermediate amplifier with of gain of approx 5. The intermediate amplifier is made with Q4 and Q9 and the gain ratio is set by R24+R9 and R18. I chooses a gain of 5 since this gives me a opamp output voltage range between 1.3V and 4.5V for a output voltage of 0 to 21V.  Also this intermediate opamp has a high poles and do not require any compensation. Also since the gain of the amplifier set the voltage range at the output of the opamp this give me the ability to use a non Rain-to-rail output OPA. But I will keep the MCP6022 since the offset is very low and the input is rail-to-rail.

The other changes are the fact that I eliminated the resistor to SUP24V that was feeding the base of the predriver NPN.  Also I swap the opamp inputs ( intermediate amplifier has positive polarity) and I added a 100-330nF capacitor over the opamp. This compensation capacitor is necessary since I noticed that the loop may become unstable in certain conditions ( when load is changing). I need such a small value ( in the hundreds range) since the opamp will amplify the effect of this capacity  ( miller effect) and the pole generated is very low.

So the new version of the schematic is here : LabPicPowerSupply_v3_SCH

There are other minor changes :

  • removed reset PIC switch
  • removed capacitors from DAC output
  • changed the positions of some PIC  IO’s
  • added protection for the input of the opamps that measure the load current ( anti-parallel diodes)
  • added the buffer before ADC voltage measurement ( VMON). before this buffer was inside the voltage loop.
  • the ILIM protection is made by changing the voltage reference ( output of the DAC)
  • small changes in the components value
  • not use the MJ3001

I made a real test of this new architecture . I used a simple breadboard and I noticed that the stability is OK . I did not had a full test under all conditions since the 2N3055 was not on the heatsink but even like that it was capable to deliver 1A at 18V output for few seconds, this means 18W !!. I  had to stop it after few seconds since the 2N3055 became too hot.

The dummy output load I made it with the BF254B device. It was the easiest and I had laying around some devices. It can be made is many different ways but in my case I do not need accuracy.

There are some aspects that I noticed also. The predriver transistor BD139 can dissipate some power. This depend on the gain current (Hfe) of the 2N3055. My transistor had a gain of 35 at Ic=1mA so this means that trough BD139 will flow approx 30mA in the worst case. If this is happening when the output voltage is at 0V ( hard short of the lab supply terminals) then this means that the predriver will dissipate 30mA*24V =  0.72W. It may not seem too much but the datasheet show that this can bring the BD139 temperature to  ~75degC above the air temperature. If the air surrounding the device is at 30C this give a junction temperature of 100C. It is high for my taste !!! so a heatsink is mandatory !

The other issue that I noted is that 5V regulator also need a heatsink. The current consumed may reach 50mA and the power dissipated can be 1W. In this conditions LM7805 can go to 65C above the air temperature. And this is continuous and not a “error condition” like in the case of BD139. So a heatsink is really necessary. Some may argue that is not bad to use them without heatsink since this is a tolerable temperature and many Chinese manufacturers do it… well it is my design and I do not want to risk.

I made also a layout tentative.  It was not easy but at least I have a workable PCB. I still need to double-check the connection of each device to be sure that it is the correct package and the footprint is matching the actual component that I have. I hope to finish this step soon so that I can start the real manufacturing of the PCB and then component soldering.

Here are all the files for version 3  (KICAD schematic and PCB)

schematic : LabPicPowerSupply_v3_SCH

BOM list : LabPicPowerSupply_v3_BOM

PCB layout : LabPicSupply_v3_PCB

Lab power supply with PIC microcontroller (2)

So I worked more on the schematic… some changes.

Surprisingly , the hardest thing now is to search for each component and to check if it matches the footprint. This will take more days.

Regarding the case I think I will use a DVD case . the buttons are matching well the function that I want to use.


The button function will be :

[-] [+] [MENU]

[down] [up] [OK]

[ON/OFF ] [ OK ]



I tried also a routing of the board… well it is hard. manual routing is a pain in the ass, . I discovered now Freerouting and I will have to play a little bit with it to see if can give good results.



Lab power supply with PIC microcontroller (1)

I just started a new project. It is a lab power supply. The main target is to do it with a microcontroler (PIC) qnd to have good enough accuracy.
My spec is 5mV per step for output voltage and 1mA per step for current. The max voltage is 20.48V and max current is 1.024A.
For this I will have a LCD screen ( 16×2 characters) and the panel will be with push burrons. I do not want to use rotary encoders.
The Lab Power Supply will use a AC-DC converter from 220V AC and will provide also some other fixed voltages like : 5V, 3.3V and maybe others (12V).
For the moment I have two old AC-DC converter from some printers (HP and Canon).
For the case I think I will use a old DVD player case since I have there all the necessary buttons and front panel.

I target to use PIC16F1789 since it is powerfull enough and has many IO pins. The ADC reading will be made with MCP3201 12bit and the DAC wil be MCP4922 dual 12bit DAC.
For the reference I intend to use MCP1541 but here I am not sure. I may also use a trimmable reference since I want to be precise for the 4.096V value.

For the current measurement I wanted to use INA210 or similar from TI but they are not cheap and hard to find. Also TI sample program is a nightmare. So I decided to use a opamp and a PNP to read the high-side current.
The opamp that I want to use is MCP6022 (2 OPA per package) . I need to use this opamp since it needs very low offset and full rail-to-rail input/output.
The other opamps that I have are not well suited for this job (some have bigger offset or/and not rail-to-rail in/out).

The ILIM loop and voltage loop are made fully in analog domain. I do not want to make it in software since may create issues later and also because I have more experience with the analog than PIC software. The other reason is that it is easier to debug and they are modular.

For the voltage divider I use a buffer since the ADC require low inpedance input source and a simple resistor divider will not work well.

I added below the full schematic that I have now. It is still a work in progress so I do not encourage anyone to think that is fully functional or that is tested. It is just a schematic made based on my knowledge.

LabPicSupply version 1 (pdf file)

LabPicSupply BOM list

Power soft switch

I want to describe here some schematics for a power switch. The soft power switch is in fact a electronic switch ( no relay, no moving parts) that can be used as a ON/OFF for a certain device.

The classical way to switch ON/OFF a device is to use a flip switch like this :

But this mechanical switch is expensive and can break  after a wile.

The other big disadvantage is that it require the mains AC line (supply line) to physically pass through that switch. So if for example you want to put the ON/OFF switch on the front panel of a device you have to go there with AC 110/220V mains. This can create problems (noise, interference…)

Beside this some people want a “fancy” ON/OFF function with only a simple push button. Like this:

So The switch is very small and can be integrated directly on the PCB board. Beside this there is very small voltages/current passing so there is no risk of electroshock.

Usually this type of application use DC voltages in the 3-24V domain. They are used often to start a board that has micro-controller or a small electronic device.

The following possibilities are shown below:

1: power_soft_switch















Improved CMOS voltage follower

The below figure show two variants of the voltage follower.

diagram A show the classical voltage follower. This stage is used in CMOS design because we need a Vgs voltage shifting or because we need a intermediate stage that have high input impedance and low output impedance. As it is easy to observe, the output impedance is 1/gm1 so it is usually in the order of Kohms.

There are many ways to improve the voltage follower  and one simple solution I will describe here.


In the B diagram the M1 transistor is having the same behaviour like in diagram A.

But now there is M2 that form a local loop. This is a negative feedback that “boost” the performance of the M1 transistor. So now the output impedance is lowered with the gain of M2.

The sink current capability is the same as in case A but the source current capability is improved. This was not a issue with schematic A but now the mechanism that deliver current to the output net is different. In the diagram A the current was flowing from VDD to drain of M1 to output pin, while in schematic B the current flows from VDD to the source of M2, drain of M2 and to the output pin.

Another difference is that the current that flow through M1 is not fixed and do not depend on the load current. This may be important in some cases where a constant Vgs for M1 is required.

Another disadvantage of the schematic B versus the schematic A is the fact that PSRR is worse. This is do to the fact that M2 has the source connected to VDD while the gate is on a high impedance net ( that depend only on the internal loop). This may be a issue in some designs. To avoid this the designer can use other tricks to solve the issue like : regulated supply (ex : LDO ) or differential paths .

CMOS current mirror with boosting

The cascodes are used generally to increasing the output impedance of a current mirror. But sometime this is not enough. After all a ideal current source has infinite impedance so we must always try to achieve this very high output impedance.
Usually to increase the output impedance a gain is needed to “boost” the performance. This “classical” way is to use a opamp or a simple MOS transistor to acheave this.
The solution that I want to present here is simple and give good results.

M1-M4 form the classical cascode topology. The M16 current flow in to M2 so the size of M2 must be bigger than M1. Usually is 2x, 4x bigger.
The input voltage for this current mirror is VGS1 = Vt+Von.
The input impedance is 1/gm1 = small = in the order of kOhms.
The output minimum voltage is Vds16+Vds2 = usually 200-400mV
The output impedance is ro2*gm3*ro3*gm16*ro16 = big = usually in the order of 100x MOhms

The best value of Vbias is Vds2+Vgs16. This can be obtained with a replica type of circuit.

CMOS Levelshifter with memory problems

I want to comment a little bit about a classical CMOS level-shifter that has a less known issue.

The level-shifter is used to transfer logic signals from a low voltage domain ( example 1V8) to a higher voltage ( ex 3V3). This level-shifter works fine in almost all applications, when 1V8 and 3V3 supply voltages are present.

But what is happening when one of the supply is missing ?

Case A : 3V3V is zero. In this case the output is forced to zero since there is no supply for inverter T7,T8.

Case B: 1V8 is missing. This is more complicated. Because the T1, T2 form a latch, they will keep the state for long time. The value is not hard defined so it may change after some time.

But the issue that I want to present is that if for example the latch had a certain state when the 1V8 was present then it will keep that state even if the 1V8 will disappear. It is the very nature of the latch to keep his data as long as possible.

So lets say that the 1V8 has present and IN=high. It means that INB=low and A=high (3V3) and B=low (zero). The OUT is low.

If the 1V8 disappear very fast , so that the IN do not have time to toggle then what is happens ? The INB stay low since there is no supply on 1V8 rail. The IN = low since there is nobody to drive this input. The circuits that are connected  to IN were supplied also by 1V8 rail. The T3 and T4 have now both the gates to VSS. So the latch T1,T2 has no reason to change his state. The 3V3 is still present so the latch keep his state. So is easy to see that the latch still give OUT=low even if there is nobody to drive the input of the level-shifter.

What is happening when the 1V8 come back ? The inverter T5,T6 keep his state until the V1V8 is high enough (>Vth) and only after that toggle to the signal on IN.

This memory effect can be a feature of a issue.

It may be considered a feature if by memorizing the state it is doing something useful in the system.

If not , then it can be considered a issue/problem/bug since sometime we want to know that 1V8 do not exist anymore and we may need some signals to be reseted.

So use this level-shifter it with great care. And if you do not need this “memory” effect, then do not use this latch type level-shifter.