my ideas in action

Improved CMOS voltage follower

The below figure show two variants of the voltage follower.

diagram A show the classical voltage follower. This stage is used in CMOS design because we need a Vgs voltage shifting or because we need a intermediate stage that have high input impedance and low output impedance. As it is easy to observe, the output impedance is 1/gm1 so it is usually in the order of Kohms.

There are many ways to improve the voltage follower  and one simple solution I will describe here.


In the B diagram the M1 transistor is having the same behaviour like in diagram A.

But now there is M2 that form a local loop. This is a negative feedback that “boost” the performance of the M1 transistor. So now the output impedance is lowered with the gain of M2.

The sink current capability is the same as in case A but the source current capability is improved. This was not a issue with schematic A but now the mechanism that deliver current to the output net is different. In the diagram A the current was flowing from VDD to drain of M1 to output pin, while in schematic B the current flows from VDD to the source of M2, drain of M2 and to the output pin.

Another difference is that the current that flow through M1 is not fixed and do not depend on the load current. This may be important in some cases where a constant Vgs for M1 is required.

Another disadvantage of the schematic B versus the schematic A is the fact that PSRR is worse. This is do to the fact that M2 has the source connected to VDD while the gate is on a high impedance net ( that depend only on the internal loop). This may be a issue in some designs. To avoid this the designer can use other tricks to solve the issue like : regulated supply (ex : LDO ) or differential paths .


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